// SPI clock divider: 16 MHz / 32 = 500 kHz
reg [4:0] spi_clk_div = 0;
wire spi_tick = (spi_clk_div == 0);
always @(posedge CLK) spi_clk_div <= spi_clk_div + 1;

// Rotating data pattern: 0xA5, 0x3C, 0x55, 0xF0, 0x0F, 0x69, 0x96, 0xCC
// SPI Mode 0 (CPOL=0, CPHA=0), MSB first
// CS# goes low for each byte, high between transfers
// MISO echoes MOSI inverted (simulated slave response)

assign PIN_1 = spi_sck;     // D0 — SCK
assign PIN_2 = spi_mosi;    // D1 — MOSI
assign PIN_3 = spi_miso;    // D2 — MISO
assign PIN_4 = spi_cs_n;    // D3 — CS#

// 9600 baud: 16,000,000 / 9600 = 1667 clocks per bit
// Sends "SAM\r\n" repeating, 8N1 format
// Start bit (0), 8 data bits LSB first, Stop bit (1)

reg [7:0] uart_9600_msg [0:4];
initial begin
    uart_9600_msg[0] = 8'h53; // 'S'
    uart_9600_msg[1] = 8'h41; // 'A'
    uart_9600_msg[2] = 8'h4D; // 'M'
    uart_9600_msg[3] = 8'h0D; // CR
    uart_9600_msg[4] = 8'h0A; // LF
end

assign PIN_5 = uart_9600_tx;  // D4 — UART 9600

// ─────────────────────────────────────────

// 115200 baud: 16,000,000 / 115200 ≈ 139 clocks per bit
// Sends 0x55 ("U") repeating — alternating bits
// Perfect pattern for scope auto-baud detection

assign PIN_6 = uart_fast_tx;  // D5 — UART 115200

// I2C clock: 16 MHz / 160 = 100 kHz (standard mode)
// Generates real I2C sequences:
//   START → Address 0x50 (Write) → ACK → Data byte → ACK → STOP
// Data byte increments each transaction (0x00, 0x01, 0x02...)
// Simulated ACKs (SDA pulled low) so decoder sees clean frames

reg [7:0] i2c_addr = 8'hA0;   // 0x50 << 1 | W = 0xA0
reg [7:0] i2c_data = 8'h00;   // Increments each frame

assign PIN_7 = i2c_scl;   // D6 — I2C SCL
assign PIN_8 = i2c_sda;   // D7 — I2C SDA

// 8-bit free-running counter at ~50 kHz
// 16 MHz / 320 = 50 kHz update rate
// Counts 0x00 → 0xFF continuously

reg [7:0] bus_counter = 0;

assign PIN_9  = bus_counter[0];  // D8  — Bit 0
assign PIN_10 = bus_counter[1];  // D9  — Bit 1
assign PIN_11 = bus_counter[2];  // D10 — Bit 2
assign PIN_12 = bus_counter[3];  // D11 — Bit 3
assign PIN_13 = bus_counter[4];  // D12 — Bit 4
assign PIN_14 = bus_counter[5];  // D13 — Bit 5
assign PIN_25 = bus_counter[6];  // D14 — Bit 6
assign PIN_26 = bus_counter[7];  // D15 — Bit 7

# Clock & LED
set_io --warn-no-port CLK    B2
set_io --warn-no-port LED    B3
set_io --warn-no-port USBPU  A3

# Left header: D0–D12
set_io --warn-no-port PIN_1  A2    # D0  — SPI SCK
set_io --warn-no-port PIN_2  A1    # D1  — SPI MOSI
set_io --warn-no-port PIN_3  B1    # D2  — SPI MISO
set_io --warn-no-port PIN_4  C2    # D3  — SPI CS#
set_io --warn-no-port PIN_5  C1    # D4  — UART 9600
set_io --warn-no-port PIN_6  D2    # D5  — UART 115200
set_io --warn-no-port PIN_7  D1    # D6  — I2C SCL
set_io --warn-no-port PIN_8  E2    # D7  — I2C SDA
set_io --warn-no-port PIN_9  E1    # D8  — Bus bit 0
set_io --warn-no-port PIN_10 G2    # D9  — Bus bit 1
set_io --warn-no-port PIN_11 H1    # D10 — Bus bit 2
set_io --warn-no-port PIN_12 J1    # D11 — Bus bit 3
set_io --warn-no-port PIN_13 H2    # D12 — Bus bit 4

# Right header: D13
set_io --warn-no-port PIN_14 H9    # D13 — Bus bit 5

# Bottom pads: D14, D15
set_io --warn-no-port PIN_25 G1    # D14 — Bus bit 6
set_io --warn-no-port PIN_26 J3    # D15 — Bus bit 7

[env:default]
board = tinyfpga-bx
top-module = top